A Two-stage approach to harmonic rejection mixing using blind interference cancelling

Current analog harmonic rejection mixers typically provide 30–40 dB of harmonic rejection, which is often not sufficient. We present a mixed analog-digital approach to harmonic rejection mixing that uses a digital interference canceler to reject the strongest interferer. Simulations indicate that, given a practical RF scenario, the digital canceler is able to improve the signal-to-interference ratio by 30–45 dB

Tunable n-path notch filters for blocker suppression: modeling and verification

N-path switched-RC circuits can realize filters with very high linearity and compression point while they are tunable by a clock frequency. In this paper, both differential and single-ended N-path notch filters are modeled and analyzed. Closed-form equations provide design equations for the main filtering characteristics and nonidealities such as: harmonic mixing, switch resistance, mismatch and phase imbalance, clock rise and fall times, noise, and insertion loss. Both an eight-path single-ended and differential notch filter are implemented in 65-nm CMOS technology. The notch center frequency, which is determined by the switching frequency, is tunable from 0.1 to 1.2 GHz. In a 50- environment, the N-path filters provide power matching in the passband with an insertion loss of 1.4–2.8 dB. The rejection at the notch frequency is 21–24 dB,P1 db> + 2 dBm, and IIP3 > + 17 dBm

D/A Resolution Impact on a Poly-phase Multipath Transmitter

In recent publications the Poly-phase multipath technique has been shown to produce a clean output spectrum for a power upconverter (PU) architecture. The technique utilizes frequency independent phase shifts before and after a nonlinear element to cancel out the harmonics and sidebands due to the nonlinearity. A major advantage of this technique is that it circumvents the need to use dedicated RF filters which makes it a potential candidate for cognitive radio transmitters. This paper addresses the requirements on the digital and mixed signal part of such a transmitter. An architecture is proposed based on complex multiplication which can be used to generate the digital multiphase signals required by the multipath technique. Due to equal phase difference of all the paths the same digital hardware could be utilized for carrying out all the phase shifts. When the digital signals pass through a D/A converter which doesn’t have a reconstruction filter, the output in this case would be amplitude discrete like that of a zero order hold. The spectrum of this amplitude discrete signal would have distortion components in it. This can be termed as quantization distortion but now in the context of limited D/A resolution. The multipath technique’s effect on harmonic cancellation, in the presence of such a quantization distortion is explored in this paper. It is shown through simulation that when using ideal phase shifts the multipath technique is able to cancel most of the harmonics produced by an amplitude discrete representation of pure sinusoids. When (upconversion) mixers are used for the second set of phase shifts then with multipath the highest quantization spurs go down with roughly 8db/bit for a single tone and around 10db/bit for two tone inputs

A Blind Interference Canceling Technique for Two-Stage Harmonic Rejection in Down-mixers

This paper presents practical experiments on a harmonic rejection down-mixer, which offers up to 75 dB of harmonic rejection, without an RF filter. The down-mixer uses a two-stage approach; the first stage is an analog multi-path/multiphase harmonic rejection mixer followed by a second stage providing additional harmonic rejection based on blind adaptive interference canceling in the discrete-time domain. The aim is to show its functional operation. The canceler cannot cope with DC offsets. The DC offsets are removed by highpass filters. The signal paths used to obtain an estimate of the interference must be designed to provide as much attenuation of the desired signal as possible. Front-end nonlinearities and DC offsets are discussed

A Discrete-Time Mixing Receiver Architecture with Wideband Harmonic Rejection

A discrete-time mixing architecture for software-defined radio receivers exploits 8 RF voltage oversampling followed by charge-domain weighting to achieve 40dB 3rd and 5th harmonic rejection without channel bandwidth limitations. Noise folding is also reduced by 3dB. A zero-IF downconverter chip in 65nm CMOS can receive RF signals up to 900MHz, with NFmin=12dB, IIP3=11dBm at <20mW power consumption including multi-phase clock generation

Experimental Verification of a Harmonic-Rejection Mixing Concept using Blind Interference Canceling

Abstract—This paper presents the first practical experiments\ud on a harmonic rejection downconverter, which offers up to 75 dB of harmonic rejection, without an RF filter. The downconverter uses a two-stage approach; the first stage is an analog multipath/ multi-phase harmonic rejection mixer followed by a second stage providing additional harmonic rejection based on blind adaptive interference canceling in the discrete-time domain. The aim is to show its functional operation and to find practical performance limitations. Measurement results show that the harmonic rejection of the downconverter is insensitive to frontend nonlinearities and LO phase noise. The canceler cannot cope with DC offsets. The DC offsets are removed by highpass filters. The signal paths used to obtain an estimate of the interference must\ud be designed to provide as much attenuation of the desired signal as possible

CMOS Transmitter using Pulse-Width Modulation Pre-Emphasis achieving 33dB Loss Compensation at 5-Gb/s

A digital transmitter pre-emphasis technique is presented that is based on pulse-width modulation, instead of finite impulse response (FIR) filtering. The technique fits well to future high-speed low-voltage CMOS processes. A 0.13 /spl mu/m CMOS transmitter achieves more than 5 Gb/s (2-PAM) over 25 m of standard RG-58U low-end coaxial copper cable. The test chip compensates for up to 33 dB of channel loss at the fundamental signaling frequency (2.5 GHz), which is the highest figure compared to literature

A Software-Defined Radio Receiver Architecture Robust to Out-of-Band Interference

In a software-defined radio (SDR) receiver it is desirable to minimize RF band-filtering for flexibility, size and cost reasons, but this leads to increased out-of-band interference (OBI). Besides harmonic and intermodulation distortion (HD/IMD), OBI can also lead to blocking and harmonic mixing. A wideband LNA [1, 2] amplifies signal and interference with equal gain. Even a low gain of 6dB can clip 0dBm OBI to a 1.2V supply, blocking the receiver. Hard-switching mixers not only translate the wanted signal to baseband but also the interference around LO harmonics. Harmonic rejection (HR) mixers have been used [3, 1, 4], but are sensitive to phase and gain mismatch. Indeed the HR in [4] shows a large spread, whereas other work only shows results from one chip [3, 1]. This paper describes techniques to relax blocking and HD/IMD, and make HR robust to mismatch